Home | Products | Time & Frequency Distribution | DOCSIS Solutions | DTI Client Reference Design Kit

DTI Client Reference Design Kit

Everything a hardware designer needs to integrate a DTI Client onto a PC circuit board

The DTI Client Reference Design Kit can transform a PC to a DTI Client via point-to-point connections between the server and each client for DOCSIS Timing Interface functionality. A single protocol initiated by the DTI server permits the client to perform frequency and time synchronization externally through the DOCSIS Timing Interface.

The DTI Client Reference Design Kit integrates a fully compliant DTI client onto a PC board for network synchronization functions.

Full Compliance with DOCSIS Timing Interface Specification

  • Physical layer requirements
  • RJ-45 physical interconnect
  • Electrical characteristics
  • Implementation of protocol
  • Support for operating characteristics
  • Support for DTI Status LED(s)
  • Loop filter bandwidth and pull-in range
  • Implementation of all operational states
  • Support for DTI Client Test Port. This includes 10.24 MHz LVDS clock, 10 kHz LVTTL frame clock, and DTI frame serialized data (LVTTL).

Testing Port
Support for 1PPS test port

Support For Redundant Connections
An optional, second DTI connection port enables redundant connections to DTI servers.

Improved stability
An optional external 10 MHz connection improves free-run stability compared with the stand-alone DTI client.

Analyze DTI Status Link and Client Behavior
Includes a register map for reading and setting various types of information relating to status of the DTI link and client behavior. I2C protocol is implemented to support reading from and writing to this register map.

Generate a Timestamp Synchronization Output Pulse
Synchronize a customer-provided DTI timestamp value (written into the register map by customer) with a DTI timestamp value received via DTI link. When the two values are equal, a pulse is generated.

Square Wave Outputs
Includes an 8 kHz LVTTL square-wave output aligned with rising edge of 1PPS output.

Supports FPGA Programming
Includes a JTAG header for FPGA programming.